Space and other radiation environments create electron hole ion pairs in the irradiated materials. In conductors and semiconductors, the electrons and holes are mobile and are quickly collected at device terminals as "photocurrents". In insulators electrons are generally much more mobile than holes. Holes can be immobilized for long periods of time ... essentially forever. The drawing illustrates the gate (polysilicon), gate insulator and bulk regions of an MOS transistor. The gate poly is colored orange, the gate insulator (silicon dioxide, generally) white and the bulk material blue. During irradiation electron-hole pairs are created uniformly in the device materials. The ion pairs that eventually result in device degradation are shown as "+" and "-" symbols in the gate insulator.

In normal CMOS logic N devices experience zero or positive gate to source/bulk-substrate bias and P devices experience zero or negative bias. Biases of either polarity can exist in mixed signal circuit, transmission gates or in series devices in the "off". The field present during irradiation causes holes to be attracted or repelled from the gate depending on the bias polarity. Electrons are much more mobile than the holes and most are collected quickly at the device terminals leaving behind a net positive charge with a "center of gravity" which tends to be located nearer to the gate or the channel region depending on the bias polarity....closer to the channel for typical N transistors and closer to the gate for typical P transistors (because of the prevalent bias polarity). The closer the charge is to the channel, the more effective it is in modulating the effective threshold voltage of the transistor. For this reason the shift of thershold voltage in N transistors tends to be quicker than for P transistors for small to moderate total doses. The drawing for this paragraph illustrates the charge location concept. When holes are trapped in the gate oxide the effect is analogous to the insertion of a battery in series with the gate lead of the device with the positive terminal at the device gate. This causes N transistors to increase in conduction ("turn on") and P transistors to decrease in conduction ("turn off").

Time and temperature play an important role in MOS total dose behavior. At very low temperatures (77K for example) virtually all holes are trapped permanently and threshold voltage shifts are very high compared to those at room temperature. Low temperature behavior is very important for cryogenic electronics e.g. infrared focal planes. At elevated temperatures holes tend to be neutralized by mobile electrons until the net trapped charge is reduced to nearly zero. It is (in general) possible to anneal out virtually all charge trapped in gate insulators by elevating the device temperature to 250C or more for several hours (overnight).

N transistors are subject to a long term mechanism known as "rebound" which compensates for hole trapping. For short irradiation periods (hours) threshold voltages move more negative. At a high enough dose or after a long enough time period, threshold voltage shifts are observed to reverse direction because of the creation of so-called interface states. If an experimental characterization is performed with a cobalt-60 radiation source where environments of 100KRads (for example) are achieved in hours, N device threshold shifts in the negative direction (toward turn-on) are observed. However, if an irradiated device is kept under bias at an elevated temperature for several hours or overnight (after irradiation), the threshold voltage is observed to return to the original value or even "rebound" higher. Since time and temperature are roughly interchangeable, the same device when irradiated in a background space environment where 100KRads is encountered over a number of years may show a monotonic INCREASE in threshold voltage because trapped charge annealing occurs on a time period comparable to the radiation period leaving only interface state generation to affect the threshold voltage shift. "Rebound" is a significant issue for long lifetime space vehicles.

As gate oxide thickness has dropped below 100 angstroms with technology scaling, threshold voltage shift has become a secondary total dose space radiation issue. Threshold voltage shift in thick oxide isolation regions has become the dominant device problem. Since threshold voltage shift is roughly proportional to the square of the oxide thickness (for oxide thickness above 100 angstroms), the thick field isolation regions experience large shifts in threshold. Just as for the gate oxides, holes tend to be trapped resulting in the attraction of electrons to the trapped holes which tends to make both N and P regions more N-type. If a P isolation region is converted to N, leakage can occur around (drain-to-source) and between N devices. Since the distance between transistors is generally much larger than the drain-to-source spacing, leakage at the edge of N transistors is the dominant effect. The leakage path between transistors can also be important. However, the channel length of the parasitic leakage transistor is much longer.

The drawing illustrates normal conduction in an N transistor prior to irradiation. The top half of the drawing is the plan view of the transistor and the red region indicates the region of current flow from drain-to-source. The bottom half of the drawing shows a cross section of the transistor taken through the center of the gate and illustrates the region of current flow (orthogonal to the page) under the gate. It illustrates the nature of the region at the edge of the transistor where the thin gate oxide makes a transition to the thick field region. The drawing is not to scale. A variety of methods are used to create the field oxide region. This drawing illustrates only one of them. However, in general, they all tend to have a transition from thin to thick oxide immediately adjacent to the edges of the transistor. The thick field region is typically over ten times the thickness of the gate oxide. The threshold voltage shift in the field could then be expected to be 100 times or more higher than that under the thin gate oxide. In the oxide transition region and into the field, the parasitic edge transistor can be thought of as several narrow transistors in parallel. As the distance is increased away from the edge of the intentional transistor, the "gate" oxide thickness increases and the INITIAL threshold voltage also increases because of the thicker oxide. The effective channel length is longer because current flow must be from the N+ drain to the N+ source in a curved path out into the transition and field region. Prior to irradiation, the increased threshold voltage(s) in the transition and field regions result in virtually zero conduction under all electrical conditions. The field inversion potential (the threshold voltage of the parasitic transistor in the field region) is typically several times higher than the maximum power supply limits.

When transistors are irradiated the threshold voltage in an N transistor is driven in the negative direction (toward conduction or turn on). For a P transistor the threshold voltage magnitude is increased (away from conduction) and the field or isolation regions are driven heavily "off". The threshold voltage shift is far higher in the edge regions where the oxide is thicker. For an N transistor, conduction immediately adjacent to the transistor edge is encouraged and the conduction would be greatest under the field region if it were not for the much longer conduction path (channel length). Consider an N transistor which is operating in the saturated channel mode of conduction [roughly where Vds > (Vgs - Vth)] prior to irradiation. The channel conduction is as indicated in the previous drawing. The gate voltage is only slightly above the threshold voltage. If an N device is irradiated and the regions of conduction are examined with increasing ionizing radiation dose while the drain current is held constant, the region of conduction will be seen to decrease under the gate and increase at the transistor edges until virtually ALL of the conduction is at the edge and extends into the field region as shown in this drawing. When the threshold voltage of the transistor regions at the edge of the N transistor approach zero volts, a logic device can no longer be turned off in typical single power supply systems (where the minimum..most negative..N gate voltage is zero). CMOS integrated circuit standby current will increase very rapidly when this condition occurs and functional failure is often observed. The phenomenon is also important in linear circuits (amplifiers, etc.) where bias currents no longer flow where intended but at the edges where the width, length and oxide thickness of the conducting transistor region is MUCH different than shown on a schematic. This can have significant impact on linear circuit performance including noise figure.

The onset of edge leakage in an N transistor is further illustrated by the drain current curves of this paragraph. Here the drain-to-source voltage of an N transistor is held at the power supply voltage (3.3 volts) while the gate voltage is swept from -1 to +3 volts. The drain current is plotted on the logarithmic vertical axis. Initially (red curve) the drain current is very low for zero gate voltage and increases logarithmically for gate voltages below the threshold voltage (up to currents of a few microamperes). Above threshold the transistor drain current is square-law with gate voltage. When the transistor is irradiated (green curve) a parasitic transistor becomes effective which is in parallel with the main channel. As the total dose is increased (blue and then purple curves), the threshold voltage in the parasitic region becomes more and more negative and the effective width of the parasitic transistor increases. At even moderate total doses (100KRads) there is virtually no conduction under the intentional gate region of the transistor until drain currents of 100s of microamperes are reached. The drain current for zero gate voltage for this device is nearly 100 microamperes even at a zero gate voltage. This behavior is typical for most commercial processes and constitutes the most significant total dose vulnerability for CMOS circuits.

Most commercial processes which support sub-micron dimensions are relatively hard to threshold voltage shifts because the oxides are thin enough that mechanisms which enhance hole neutralization are available. Most commercial process are, however, not very hard to edge effects. Some radiation hard processes HAVE been developed which will satisfy virtually any space requirement. However, the economics are not favorable to the survival of companies that attempt to make a business out of radiation hard technology. The alternative is to use commercial technologies for space environments with devices that are "hard by device design" rather than hard by technology design. Some of the possibilities are covered under the section entitled SPACE RADIATION HARDENING.