Most commercial silicon semiconductor processes create transistors by the implantation of dopants into a bulk silicon wafer. The drawing on the right shows N and P MOS transistors in an "N-Well process. The N-FETs are formed in the bulk material (or in a twin P-well in the P- substrate). The P transistors are formed in an "N-Well" which is implanted into the substrate. One electrode of the N and P transistors is shown connected to the most positive (V+) or most negative (V-) power supply ... typical of CMOS logic. The N-Well and substrate potentials are controlled by connecting a N+ contacts in the N-Well to the most positive power supply and P+ contacts in the substrate to the most negative power supply. The MOSFET gates are not shown and the drawing is not to scale.

Parasitic NPN and PNP transistors are also created as shown. Under normal electrical conditions the bipolar transistors do not conduct because their base is tied to their respective emitters by well and substrate ties. However, a lateral spreading resistance is present in the structures as indicated by the resistor symbols. If the silicon material is ionized by radiation (light, gamma, X-ray, cosmic rays, heavy ions, etc.) photocurrents will flow in all P/N junctions. A review of the drawing shows that collector current in the PNP transistor will flow into the base material of the NPN and collector current from the NPN will flow in the base material of the PNP. These current paths form a positive feedback path much like a silicon controlled rectifier (SCR). Once currents are initiated, it is possible for them to regenerate to high values if the voltage dividers formed by the spreading resistors are appropriate and the current gains of the parasitic bipolar devices are high enough. Functional failure or burnout is possible. Latch up can also be initiated by electrical stimulus at integrated circuit connections to the outside world. For example, if the two terminals of the FETs shown in the drawing are connected to each other and a package pin, an electrical excursion imposed on that pin above or below the power supply will forward bias one of the two drains which will then act as a bipolar emitter and initiate bipolar latch path currents. Space radiation from heavy ions is a particularly effective source of ionization currents and is a major threat to spacecraft operation.

It is not necessary to encircle each N and P MOs transistor individually. Clusters of N and P FETs can be included inside a contact ring to break the latch path. However, substrate potential control is important to the operation of FETs and it is good design practice to provide well and substrate ties close to all active elements.

Fortunately, structures are available in standard CMOS processes which can eliminate latch up. This is done by reducing the base-to-emitter spreading resistance to a level which is so low that the base-emitter junction cannot be forward biased because of ohms law. The drawing for this paragraph shows well and substrate contact rings that completely circle a P and an N FET. When sensible geomety is used in normal processes the rings provide a low enough resistance path from the emitter to the base of the parasitic bipolar transistors that latch up cannot occur. A continuous ring cannot be formed unless the gate contact to the transistors crosses the ring in metal rather than poly. This causes a layout density penalty. A continuous ring is NOT necessary to eliminate most latch up paths. However, it is desirable for total dose hardening as discussed under the section titled SPACE RADIATION HARDENING.

Latch up can also be eliminated by utilizing wafers with a thin epitaxial layer which is grown on a heavily doped bulk substrate (generally P- on P+). The P+ substrate is connected to the most negative power supply tying the parasitic NPN base firmly to its emitter. Not ALL epitaxial processes use a thin enough epitaxial layer to be effective. All epitaxial processes are not necessarily immune to latch up.

Dielectrically isolated semiconductor processes are also very effective in the elimination of latch up e.g. SOI/SOS. In these processes a thin layer of silicon is formed on an insulator and individual transistor are isolated in the lateral direction by the formation of "islands" by etching the epitaxial layer away to the insulating substrate. Unfortunately, SOI/SOS processes are not readily available from semiconductor foundries which can be counted on for timely and cost effective support.