Most commercial silicon semiconductor processes now produce gate insulators that are quite hard to total dose radiation simply because the technologies have scaled to the point where gate oxide thickness are less than 100 angstroms ... sometimes considerably less. However, edge leakage still remains to be a major vulnerability as discussed under TOTAL DOSE - SPACE RADIATION. Fortunately edge leakage (drain-to-source) can be eliminated by construction "edgeless" devices. The drawing for this paragraph illustrates an edgeless device. The drawing is not to scale and does not represent a particularly elegant layout but is meant to convey the basic concept of edgeless devices. The transistor gate (orange) forms a continuous ring between the drain and source (purple). (drain and source are interchangeable.) The ring cannot be continuous if the gate material (poly) is used to connect to regions outside of the outer limits of the transistor because the gate masks the drain/source implant. The gate is instead brought out of the local transistor on a metal layer (light blue) which is contacts the gate over thick oxide (black box) over the source (or drain) region. Transistors created by this method are amazingly hard to total dose radiation and environments in the megarad region or higher can be tolerated when fabricated with inexpensive commercial processes. This technique may appear to have major density penalties. However, the layout is surprisingly efficient and most general purpose or mixed signal electronics can be implemented by the technique as well as gate arrays and standard cells. This technique makes affordable total dose hard space electronics a reality.

Latch up must also be addressed for space electronics. If well/substrate rings are used in conjunction with edgeless (reentrant) transistors, both total dose and latch up vulnerabilities can be solved with a unified layout approach. (See the section untitled LATCH UP.)

A variety of processing approaches which have been specifically developed to address total dose harness. Unfortunately, these processes are not readily available from semiconductor foundries which can be counted on for timely and cost effective support.